Field of the Invention
The present invention relates to a signal readout circuit, and more particularly, to a signal readout circuit provided in each column of a solid-state imaging device and a method for controlling the signal readout circuit.
Description of Related Art
In recent years, complementary metal oxide semiconductor (CMOS) image sensors have been gathering attention and put to practical use as solid-state imaging devices. A CMOS image sensor can easily cope with SOC (system on chip) for realizing multi-functional image sensors since a CMOS image sensor can be manufactured using the same manufacturing process as ordinary semiconductors, compared to charge coupled device (CCD) image sensors which are manufactured using a dedicated manufacturing process.
Thus, a column-parallel AD conversion-type configuration in which a signal processing circuit having an analog-to-digital (AD) converter that converts analog signals to digital signals is disposed in each column of a pixel array is generally used in CMOS image sensors in which the product (hereinafter referred to as “image output data rate”) of a pixel count and a frame rate is large, for example. In the column-parallel AD conversion-type CMOS image sensor, since all signal processing circuits including the AD converter are disposed in each column of the pixel array, each signal processing circuit has a layout shape that extends in a column direction as a pixel interval (pitch) decreases. Thus, for example, in a CMOS image sensor having a small number of pixels and a small imaging surface, the central position of a chip is greatly shifted from the central position of an imaging surface (pixel array), and optical design is difficult in a system on which the column-parallel AD conversion-type image sensor is mounted. Moreover, since the same number of signal processing circuits as the number of columns of the pixel array are disposed in the column-parallel AD conversion-type CMOS image sensor, the area occupied by the signal processing circuits in the chip increases (the area corresponds to a product of the number of columns and the area of one signal processing circuit). Thus, the area of the entire chip of the CMOS image sensor (hereinafter referred to as a “chip area”) increases, which is not desirable for reducing the chip size.
On the other hand, a global AD conversion-type configuration in which one AD converter is disposed to be shared by all signal processing circuits rather than providing the AD converter in each signal processing circuit disposed in each column of a pixel array is generally used in CMOS image sensors which have a low image output data rate and require low power consumption, for example. The global AD conversion-type CMOS image sensor uses a column-double sampling method in which a signal processing circuit (not including the AD converter) disposed in each column of the pixel array samples two voltages including a pixel floating diffusion layer reset signal voltage (hereinafter referred to as a reset signal voltage) VR and a pixel optical signal voltage (hereinafter referred to as an optical signal voltage) VS output from pixels of a corresponding column to perform correlated double sampling. The optical signal voltage VS also includes a reset signal voltage VR generated after the pixel floating diffusion layer is reset. Thus, correlated double sampling is performed to obtain a pixel signal voltage indicating only subject light to which pixels are exposed by removing the reset signal voltage VR included in the optical signal voltage VS.
Since the column-double sampling-type signal processing circuit may include only two sampling capacitors as major components, the length in the column direction of the layout shape of the signal processing circuits disposed in each column can be reduced. Thus, the global AD conversion-type CMOS image sensor has a remarkable advantage that an increase in the chip area can be suppressed more than the column-parallel AD conversion-type CMOS image sensor and the chip size can be reduced.
For example, Japanese Unexamined Patent Application, First Publication No. 2004-186790 discloses a technique related to a solid-state imaging device which includes a column-double sampling-type signal processing circuit (see FIG. 9A) in each column of a pixel array. In the conventional signal processing circuit illustrated in FIG. 9A, a sampling operation of sampling two signal voltages output from pixels and a signal transferring operation of transferring the sampled two signal voltages are performed based on a clamp voltage VCL connected via switches S3 and S4 driven by a clamp signal φCL. That is, the signal processing circuit illustrated in FIG. 9A is a signal processing circuit that is configured to first convert a signal voltage output from each pixel 1 to an electric charge, then convert the electric charge to a voltage, and read the voltage.
Here, the operation of the conventional signal processing circuit disclosed in Japanese Unexamined Patent Application, First Publication No. 2004-186790 will be described with reference to the timing chart illustrated in FIG. 9B. First, the sampling operation involves sequentially driving sampling signals φSHR and φSHS so that a switch S1 is connected to a sampling capacitor CSR and a switch S2 is connected to a sampling capacitor CSS. As a result, an electric charge corresponding to a potential difference between the clamp voltage VCL and a reset signal voltage VR or an optical signal voltage VS output from the pixels 1 to a column circuit 7 via a pixel output line VCOLPIX is stored (sampled) in the sampling capacitors CSR and CSS.
The signal transferring operation involves driving a select signal φSEL to connect one set of terminals of the sampling capacitors CSR and CSS to a charge amplifier circuit 8 via switches S5 and S6. After that, a driving signal φCB is driven to connect the other set of terminals of the sampling capacitors CSR and CSS via a switch S0 so that the potential of the other set of terminals becomes an intermediate potential between the reset signal voltage VR and the optical signal voltage VS.
As a result, an electric charge corresponding to a change in the potential of the other terminal of the sampling capacitor CSR (that is, an electric charge corresponding to a potential difference between the intermediate potential and the potential of the reset signal voltage VR) is discharged from one terminal of the sampling capacitor CSR and is transferred to one terminal of a feedback capacitor CFB1 connected to one input terminal of a charge amplifier EAMP. Moreover, an electric charge corresponding to a change in the potential of the other terminal of the sampling capacitor CSS (that is, an electric charge corresponding to a potential difference between the intermediate potential and the potential of the optical signal voltage VS) is discharged from one terminal of the sampling capacitor CSS and is transferred to one terminal of a feedback capacitor CFB2 connected to the other input terminal of the charge amplifier EAMP.
As a result, an electric charge having the opposite polarity from the electric charge transferred to one terminal of the feedback capacitor CFB1 is supplied from one output terminal of the charge amplifier EAMP to the other terminal of the feedback capacitor CFB1. Thus, one output terminal of the charge amplifier EAMP has a reset signal voltage VOM having a potential corresponding to the supplied electric charge (that is, a potential proportional to an electric charge corresponding to a potential difference between the clamp voltage VCL and the reset signal voltage VR sampled to the sampling capacitor CSR) (that is, a potential proportional to the reset signal voltage VR). Moreover, an electric charge having the opposite polarity from the electric charge transferred to one terminal of the feedback capacitor CFB2 is supplied from the other output terminal of the charge amplifier EAMP to the other terminal of the feedback capacitor CFB2. Thus, the other output terminal of the charge amplifier EAMP has an optical signal voltage VOP having a potential corresponding to the supplied electric charge (that is, a potential proportional to an electric charge corresponding to a potential difference between the clamp voltage VCL and the optical signal voltage VS sampled to the sampling capacitor CSS) (that is, a potential proportional to the optical signal voltage VS).
After that, a difference between the reset signal voltage VOM output from one output terminal of the charge amplifier EAMP and the optical signal voltage VOP output from the other output terminal is calculated to obtain a signal component Vsig of only subject light to which the pixels 1 are exposed.
Moreover, for example, “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems.” by Sunetra K. Mendis, et al., IEEE Journal of Solid-State Circuits, Vol. 32, No. 2, February, 1997, hereinafter referred to as a “Non-Patent Literature 1”, proposes a solid-state imaging device in which a signal processing circuit (see FIG. 10A) including two voltage amplifier circuits is provided in each column of a pixel array. The conventional signal processing circuit illustrated in FIG. 10A performs a sampling operation and a signal transferring operation based on the ground potential. That is, the signal processing circuit illustrated in FIG. 10A is a signal processing circuit configured to read the signal voltages output from the respective pixels 1 in the form of voltage.
Here, the operation of the conventional signal processing circuit proposed in Non-Patent Literature 1 will be described with reference to the timing chart illustrated in FIG. 10B. First, the sampling operation involves sequentially driving a sampling signal φSHR and a sampling signal φSHS so that a switch S1 is connected to a sampling capacitor CSR and a switch S2 is connected to a sampling capacitor CSS. Moreover, an electric charge corresponding to a potential difference between the ground potential and the reset signal voltage VR or the optical signal voltage VS output to the column circuit 9 via the pixel output line VCOLPIX from the pixels 1 (that is, the voltage of the reset signal voltage VR or the optical signal voltage VS) is sampled to the sampling capacitors CSR and CSS. As a result, an amplified voltage of the reset signal voltage VR sampled to the sampling capacitor CSR is output from a voltage amplifier CAMP1 and an amplified voltage of the optical signal voltage VS sampled to the sampling capacitor CSS is output from a voltage amplifier CAMP2.
The signal transferring operation involves driving a select signal φSEL to connect switches S5 and S6 to output a reset signal voltage VOM obtained by the voltage amplifier CAMP1 amplifying the reset signal voltage VR and an optical signal voltage VOP obtained by the voltage amplifier CAMP2 amplifying the optical signal voltage VS. A difference between the reset signal voltage VOM and the optical signal voltage VOP output by the voltage amplifiers CAMP1 and CAMP2, respectively, is calculated to obtain a signal component Vsig of the pixels 1.
After that, in the conventional signal processing circuit proposed in Non-Patent Literature 1, in order to read signals with higher accuracy, a driving signal φCB is driven to connect one set of terminals of the sampling capacitors CSR and CSS via a switch S0 so that the potential of one set of terminals becomes an intermediate potential between the reset signal voltage VR and the optical signal voltage VS. As a result, an amplified voltage of the intermediate potential between the reset signal voltage VR and the optical signal voltage VS is output from the voltage amplifiers CAMP1 and CAMP2.
An operation circuit (not illustrated) at a subsequent stage of the signal processing circuit subtracts the output amplified voltage of the intermediate potential from the voltage of the signal component Vsig obtained through the difference operation. In this way, the conventional signal processing circuit proposed in Non-Patent Literature 1 can obtain a signal component having higher accuracy in which an offset variation of the voltage amplifiers CAMP1 and CAMP2 included in the signal component Vsig is cancelled. The readout method used in the conventional signal processing circuit proposed in Non-Patent Literature 1 is a readout method called a delta-difference sampling (DDS) scheme.